As the number of transistors on a chip increases on every generation, old processor design recipes are less valuable to keep power consumption to reasonable levels. Today’s processors are somehow less focused on clock frequency, ILP (instruction level parallelism) and single thread performance, in favor of other types of parallelism as DLP (data level parallelism) and TLP (thread level parallelism). As a result, HPC applications cannot only rely on the compiler and the micro-architecture anymore, but it is programmer’s responsibility to explicitly express parallelism in order to exploit the full performance capabilities of the system underneath, even on a single node.
In this tutorial we will learn about the Many Integrated Core (MIC) architecture and Intel® Xeon PhiTM coprocessors, and also about the key pillars that make this architecture highly suitable for parallel applications. We will also review the different parallel programming models available for native and offload execution, as well as best known methods for parallelization and optimization that enable the programmer to achieve the best application performance out of this platform. Finally, we will provide a comprehensive overview of Intel® Parallel XE 2015 tool suite, which simplifies the design, development, and tuning of parallel applications running on Intel® Xeon® processors and Intel® Xeon PhiTM coprocessors. The tutorial will be accompanied by a demo of Intel Parallel Studio XE 2015 tool suite (if time permits).
We have three major goals for this tutorial:
- Provide attendees with a clear overview of Intel Many Integrated Core (MIC) architecture and Intel® Xeon PhiTM coprocessor, and the main differences w.r.t. Intel® Xeon® processor architecture.
- Review in some depth the parallelism fundamentals that will allow to extract maximum application performance from an Intel® Xeon PhiTM coprocessor.
- Cover the latest release of Intel Parallel Studio XE tool suite, which simplifies the design, development, and tuning of parallel applications running on Intel® Xeon® processors and Intel® Xeon PhiTM coprocessors.
The concepts presented in this tutorial are not new, and they are inspired on existing online material available to everyone. Nevertheless, the actual tutorial contents, screenshots, and case studies have been developed by the authors of this tutorial.
Title: Bring your application to a new era: parallelization and optimization for the Intel® Xeon PhiTM coprocessor
Authors: Manel Fernández, Richard Paul, and Roger Philp (Bayncore Ltd.)
Speaker: Manel Fernández (Bayncore Ltd.)
Date: 4th February 2015
Location: Faculty of Chemistry (UB), C/ Martí i Franqués 1, 08028 Barcelona, Spain.